OF PCI Bus Addresses

This is the format that OpenFirmware uses for PCI bus addresses (in the reg property and similar places). For further information, see the PCI Bus Binding to Open Firmware, which you can get on the Open Firmware working group's site or one of its mirrors.

A PCI bus address is 3 cells, which the spec labels phys.high, phys.mid, and phys.lo. phys.mid and phys.lo are a 64-bit offset or memory address (for 32-bit addresses, phys.mid is ignored, and must be 0). phys.high tells where the device is attached to the PCI bus. Bitwise, it looks like this:

npt000ss bbbbbbbb dddddfff rrrrrrrr

Where:

• n NOT relocatable (0 if relocatable, 1 if fixed).
• p prefetchable (cacheable).
• t aliased (Non-Relocatable I/O), below 1 MB (Memory), or below 64 KB (relocatable I/O).
• s 2-bit address space (Configuration [00], I/O [01], 32-bit Memory [10], 64-bit Memory [11]).
• b 8-bit bus number.
• d 5-bit device number.
• f 3-bit function number.
• r 8-bit register number.